Logic simulators enable a logic circuit to be modeled and circuit behavior to be predicted without the construction of the actual circuit. As circuit complexity increases, the time required for logic simulation also increases. In many cases, a logic simulation run must be performed numerous times as the designer searches for a design problem. Most often, these design problems are functional in nature and detailed timing information is not necessary during the successive simulation runs. However, once the functional problems have been located and corrected, the designer needs to be able to perform logic simulation with detailed timing information. If the timing simulation is performed on the same "netlist" with the same simulator as was used for the unit delay simulation, the possibility of translation error is eliminated. The present invention allows the functional errors to be located with extremely fast "unit delay" mode simulation and allows detailed timing simulation to be performed on the same circuit "netlist" and device models.
Prior art logic simulation systems have been designed to operate in either a unit delay mode as described in U.S. Pat. No. 4,306,286 to Cocke et al, or a time wheel simulation mode as described in U.S. Pat. No. 4,656,580 to Hitchcock et al. The time wheel simulators are able to handle devices with unit delay, however, there is no significant performance improvement when all of the devices in a logic circuit are unit delay. This is due to the fact that the prior art time wheel simulators treat the unit delay devices in the same manner as multiple unit delay devices. The present invention supports a time queue management algorithm which is optimized for unit delay without sacrificing the ability to perform detailed timing simulation. The circuit designer is able to select between the unit delay mode for fast functional simulation, and the multiple unit delay mode for detailed timing simulation.